The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
The photolithography step of semiconductor production is a complex process which can generally be divided into an eight-step procedure including vapor prime, in which the surface of the wafer substrate is cleaned, dehydrated and primed to promote adhesion between the photoresist material and the substrate surface; spin coating, in which a quantity of liquid photoresist is applied to the substrate either before or during rotation of the substrate; soft bake, in which most of the solvent in the resist is driven off by heating the substrate; alignment and exposure, in which a mask or reticle corresponding to the desired circuit pattern is aligned to the correct location on the substrate and light energy is applied through the mask or reticle onto the photoresist to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the substrate; post-exposure bake; develop, in which the soluble areas of photoresist are dissolved by liquid developer, leaving visible islands and windows corresponding to the circuit pattern on the substrate surface; hard bake, in which the remaining photoresist solvent is evaporated from the substrate; and develop inspect, in which an inspection is carried out in order to verify the quality of the resist pattern. Resists which are determined to be defective can be removed through resist stripping for re-processing of the substrate. Those resists which are determined not to be defective are subjected to etching, in which those areas of a conductive layer on the substrate not covered by the photoresist are etched and those areas covered by the photoresist are protected, leaving the circuit pattern in the conductive layer on the substrate.
Conventional methods of inspecting the developed photoresist pattern include both in-line SEM (scanning electron microscopy) and off-line SEM. However, use of in-line SEM, an ADI (after development inspection) micrograph of which is generally indicated by reference numeral 10 in FIG. 1, reveals only a top view of the photoresist pattern, including the parallel ridges or islands 12 and intervening trenches 14. The in-line SEM is incapable of providing a detailed sidewall profile or line-width data of the photoresist pattern.
An ADI scanning electron micrograph of an off-line SEM is generally indicated by reference numeral 16 in FIG. 2 and shows the photoresist pattern profile, which includes a layer of photoresist 20 deposited on the wafer substrate 18 and the photoresist ridges or islands 22 extending from the photoresist layer 20 and separated by trenches 24. Unlike the in-line SEM, the off-line SEM is capable of providing both a sidewall profile and line-width data of the ridges 22 and trenches 24, including such information as the linewidth “A” of each ridge 22 and the width “B” of each trench 24, for example, as shown in FIG. 2. However, one of the limitations of the off-line SEM procedure is that the fixation process for fixing or stabilizing the photoresist profile on the wafer substrate 18 for scanning electron microscopy tends to alter, distort or damage the ridges or islands 22 of the photoresist. Consequently, the off-line SEM is incapable of providing the exact dimensions of the islands 22, the trenches 24 and other characteristics of the photoresist pattern profile. Accordingly, a new and improved method is needed for accurately measuring the exact linewidth and other dimensions of a photoresist pattern without damaging, distorting or altering the photoresist profile, which otherwise tends to render a faulty reading of the photoresist pattern dimensions.
An object of the present invention is to provide a new and improved method for measuring the various dimensions of a photoresist pattern.
Another embodiment of the present invention is to provide a new and improved method which prevents the necessity of scrapping wafers due to defective photoresist patterns.
Still another object of the present invention is to provide a new and improved method which expedites substrate processing.
Yet another object of the present invention is to provide a new and improved method which avoids distortion or damage of photoresist profiles on substrates in the fixing of a photoresist pattern for dimension measurement.
Yet another embodiment of the present invention is to provide a new and improved method for measuring dimensions of a photoresist pattern on a substrate, which method includes fixing or stabilizing the photoresist pattern profile and using transmission electron microscopy (TEM) to measure the linewidth and other dimensions of the profile.
Another object of the present invention is to provide a new and improved method for measuring dimensions of a photoresist pattern on a substrate, which method includes fixing or stabilizing the photoresist pattern profile on the substrate typically using a spin-on glass or a sputter oxide procedure and subjecting the fixed photoresist pattern profile to microscopy for measurement of the profile dimensions.
A still further object of the present invention is to provide a new and improved method which utilizes spin-on glass or sputter oxide to fix a photoresist pattern profile on a substrate and transmission electron microscopy to measure the various dimensions of the profile.